Job Description

Our client is seeking a highly skilled and experienced Physical Design Principal Engineer to join their dynamic team. In this critical role, you will oversee the entire System-on-Chip (SoC) implementation and verification process, from RTL-to-GDS. Your responsibilities will include floor planning, place and route, clock tree synthesis (CTS), static timing analysis (STA), and physical verification (PV/EMIR/Noise/SigEM) cleanup and signoff. You will contribute to cutting-edge projects within a leading fabless wireless semiconductor platform company, specializing in ultra-low-power wireless radio solutions.

Location:  San Diego, CA

Duration:  Direct hire/Fulltime 

Pay Rate: Up to $220k (depending on experience) 

Key Responsibilities:

• Execute complete physical implementation at block and chip levels.
• Perform synthesis and physical implementation tasks, including floor-planning, power delivery, place & route, timing noise analysis, physical verification, and IR/RV analysis.
• Collaborate with the SoC design team to conduct architectural feasibility studies and establish design targets for timing, power, and area.
• Analyze floorplan quality, customized clock tree structures, and place & route efficiency.
• Implement ECOs for timing closure and resolve Signal EM/Noise and Power IR/EM issues.
• Conduct DRC/LVS/ERC/ANTENNA analysis and ensure thorough cleanup.
• Lead timing verification and signoff, along with final physical verification and signoff.

Job Requirements

Required Skills / Qualifications:

• Master's degree in Electrical/Computer Science Engineering with 12+ years of industry experience, or a Bachelor's degree with 18+ years of industry experience.
• Proven expertise in Netlist (or RTL)-to-GDS physical implementation.
• Comprehensive knowledge of major EDA tools and design flows.
• Hands-on experience with TSMC N22 or below technology nodes.
• Extensive experience in chip integration and signoff processes.
• Proficiency in programming with Perl and TCL.

Preferred Skills / Qualifications:

• Deep understanding of low-power implementation methodologies.
• Advanced knowledge of timing signoff methodologies.
• Familiarity with Design-for-Test (DFT) concepts such as BSCAN, MBIST, and SCAN, and their impact on physical design flows.
• Demonstrated ability to independently execute Netlist-GDS place & route and signoff tasks.
• Successful track record in managing multi-million gate design production tapeouts.

Aleron companies (Acara Solutions, Aleron Shared Resources, Broadleaf Results, Lume Strategies, TalentRise, Viaduct) are Equal Employment Opportunity and Affirmative Action Employers. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender identity, sexual orientation, national origin, genetic information, sex, age, disability, veteran status, or any other legally protected basis. The Aleron companies welcome and encourage applications from diverse candidates, including people with disabilities. Accommodations are available upon request for applicants taking part in all aspects of the selection process.

Applicants for this position must be legally authorized to work in the United States. This position does not meet the employment requirements for individuals with F-1 OPT STEM work authorization status.

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